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2024-10-29

数逻实验2——实现数码管动态控制显示器

数码管闪烁的原理

七段数码管是一种常见的数显装置，由7个独立的发光二极管组成，用来显示数字0到9。每个数码管通常有7个段（a到g），通过控制每一段的点亮或熄灭，可以组合成不同的数字。

数码管的段位命名

a: 顶部
b: 右上
c: 右下
d: 底部
e: 左下
f: 左上
g: 中间

这7段可以组合成不同的图形来显示数字0到9。

每段可以点亮（1）或熄灭（0）。

一个8位的二进制数用于控制7段数码管的显示（通常第8位用作小数点控制）。

设计文件led_display_ctrl.v

完整代码

`timescale 1ns/1ps
module led_display_ctrl #(
    parameter ZERO         = 8'h03,
    parameter ONE          = 8'h9f,
    parameter TWO          = 8'h25,
    parameter THREE        = 8'h0d,
    parameter FOUR         = 8'h99,
    parameter FIVE         = 8'h49,
    parameter SIX          = 8'h41,
    parameter SEVEN        = 8'h1f,
    parameter EIGHT        = 8'h01,
    parameter NINE         = 8'h09,
    parameter FREQ_CLK_DIV = 99999,     /* Clock divider for 2ms */
    parameter FREQ_S2      = 9999999    /* Frequency divider for 0.1s */
)
(
    input wire clk,
    input wire rst,
    input wire s_3,
    input wire s_2,
    input wire [7:0] dip_switch,
    output reg [7:0] led_en,
    output reg [7:0] led_cx
);

    /* Signals and registers */
    wire pos_edge_s3_debounce, pos_edge_s2;     /* Debounced rising edge signals */
    reg clk_div;                                /* Divided clock (2ms) */
    reg [31:0] cnt, cnt_s2, cnt_s3;             /* Counters */
    reg [7:0] cnt_s2_d1;                        /* Counts from 1 to 20 */
    reg [7:0] display_digits [0:4];             /* Display data registers for 5 digits */
    
    /* Shift registers for edge detection */
    reg [2:0] shift_reg_s2, shift_reg_s3, status;
    reg [31:0] s3_counter_stable;               /* Debounce counter for stable s3 signal */
    wire s3_stable = (s3_counter_stable >= 150000); /* 15ms debounce delay (assuming 10MHz clock) */
    reg s3_sampled;                             /* Final debounced signal for s3 */

    /* Count the number of dip switch bits that are '1' */
    wire [3:0] num_ones = dip_switch[0] + dip_switch[1] + dip_switch[2] + dip_switch[3] + 
                          dip_switch[4] + dip_switch[5] + dip_switch[6] + dip_switch[7];

    /* Edge detection for s2 */
    always @(posedge clk or posedge rst) begin
        if (rst)
            shift_reg_s2 <= 3'b000;
        else
            shift_reg_s2 <= {shift_reg_s2[1:0], s_2};
    end
    assign pos_edge_s2 = ~shift_reg_s2[2] & shift_reg_s2[1];

    /* Edge detection for s3 (with debounce) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            shift_reg_s3 <= 3'b000;
        else
            shift_reg_s3 <= {shift_reg_s3[1:0], s_3};
    end

    /* Debounce logic for s3 */
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            s3_counter_stable <= 0;
            s3_sampled <= 0;
        end else if (shift_reg_s3[1] == shift_reg_s3[2]) begin
            /* If s3 signal remains unchanged, increment debounce counter */
            if (s3_counter_stable >= 150000) begin
                s3_sampled <= shift_reg_s3[1]; /* Capture stable s3 signal after 15ms */
            end else begin
                s3_counter_stable <= s3_counter_stable + 1;
            end
        end else begin
            /* If s3 signal changes, reset debounce counter */
            s3_counter_stable <= 0;
        end
    end

    /* Use debounced signal for edge detection of s3 */
    assign pos_edge_s3_debounce = ~s3_sampled & status[1];

    /* Count for 0.1s interval (s2) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2 <= 0;
        else if (cnt_s2 >= FREQ_S2)
            cnt_s2 <= 0;
        else
            cnt_s2 <= cnt_s2 + 1;
    end

    /* Count from 1 to 20 */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2_d1 <= 0;
        else if (pos_edge_s2)
            cnt_s2_d1 <= 0;
        else if (cnt_s2_d1 < 20 && cnt_s2 >= FREQ_S2)
            cnt_s2_d1 <= cnt_s2_d1 + 1;
    end

    /* Count s3 presses */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s3 <= 0;
        else if (cnt_s3 < 99 && pos_edge_s3_debounce)
            cnt_s3 <= cnt_s3 + 1;
    end

    /* Convert digit value to 7-segment display format */
    function [7:0] digit_to_segs;
        input [3:0] digit;
        case (digit)
            4'h0: digit_to_segs = ZERO;
            4'h1: digit_to_segs = ONE;
            4'h2: digit_to_segs = TWO;
            4'h3: digit_to_segs = THREE;
            4'h4: digit_to_segs = FOUR;
            4'h5: digit_to_segs = FIVE;
            4'h6: digit_to_segs = SIX;
            4'h7: digit_to_segs = SEVEN;
            4'h8: digit_to_segs = EIGHT;
            4'h9: digit_to_segs = NINE;
            default: digit_to_segs = ZERO;
        endcase
    endfunction

    /* Update display digits */
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            display_digits[0] <= ZERO;
            display_digits[1] <= ZERO;
            display_digits[2] <= ZERO;
            display_digits[3] <= ZERO;
            display_digits[4] <= ZERO;
        end else begin
            /* Update the display based on current counts and dip switch inputs */
            display_digits[0] <= digit_to_segs(cnt_s2_d1 % 10);
            display_digits[1] <= digit_to_segs(cnt_s2_d1 / 10 % 10);
            display_digits[2] <= digit_to_segs(cnt_s3 % 10);
            display_digits[3] <= digit_to_segs(cnt_s3 / 10 % 10);
            display_digits[4] <= digit_to_segs(num_ones);
        end
    end

    /* Clock divider (2ms) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end

    /* Generate 2ms clock */
    always @(posedge clk or posedge rst) begin
        if (rst)
            clk_div <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            clk_div <= ~clk_div;
    end

    /* Update led_cx and led_en for 7-segment display */
    always @(posedge clk_div or posedge rst) begin
        if (rst) begin
            led_cx <= ZERO;
            led_en <= 8'b11111110;
        end else begin
            case (led_en)
                8'b01111111: led_cx <= NINE;
                8'b10111111: led_cx <= ZERO;
                8'b11011111: led_cx <= display_digits[4]; /* Display num_ones */
                8'b11101111: led_cx <= display_digits[3]; /* Tens digit of s3 press count */
                8'b11110111: led_cx <= display_digits[2]; /* Units digit of s3 press count */
                8'b11111011: led_cx <= display_digits[1]; /* Tens digit of s2_d1 */
                8'b11111101: led_cx <= display_digits[0]; /* Units digit of s2_d1 */
                8'b11111110: led_cx <= ONE;               /* Default display */
                default: led_cx <= ZERO;
            endcase
            /* Rotate the enable signal to switch between digits */
            led_en <= {led_en[0], led_en[7:1]};
        end
    end
endmodule

第一行

1	timescale 1ns/1ps

作用：这个语句用来定义仿真的时间单位。

模块定义

module led_display_ctrl #(
    parameter ZERO         = 8'h03,
    parameter ONE          = 8'h9f,
    parameter TWO          = 8'h25,
    parameter THREE        = 8'h0d,
    parameter FOUR         = 8'h99,
    parameter FIVE         = 8'h49,
    parameter SIX          = 8'h41,
    parameter SEVEN        = 8'h1f,
    parameter EIGHT        = 8'h01,
    parameter NINE         = 8'h09,
    parameter FREQ_CLK_DIV = 99999,     /* Clock divider for 2ms */
    parameter FREQ_S2      = 9999999    /* Frequency divider for 0.1s */
)
(
    input wire clk,
    input wire rst,
    input wire s_3,
    input wire s_2,
    input wire [7:0] dip_switch,
    output reg [7:0] led_en,
    output reg [7:0] led_cx
);

这段代码定义了一个名为 led_display_ctrl 的模块。模块是 Verilog 中的基本单元，相当于其他语言中的函数或类。这个模块有参数、输入信号、输出信号。
#(...)部分：这是模块的参数列表。参数是可以传入模块的一些常量，用于调整模块的行为。这里的参数包括：
- ZERO 到 NINE：这些参数定义了七段数码管显示数字0到9的编码。(详情了解数码管闪烁的原理)
- FREQ_CLK_DIV：定义了时钟分频器的值，用来生成2毫秒的时钟信号。为了控制数码管的刷新频率。
- FREQ_S2：定义了生成0.1秒时钟间隔的分频器值。
input wire ...：这些是输入信号，表示模块可以接受哪些信号输入。
- clk：时钟信号，这是一个周期性高低变化的信号，电路的所有行为都会同步到它。
- rst：复位信号，当它为高电平时，模块会复位所有状态。
- s_3、s_2：按钮或开关的输入信号。
- dip_switch：8位拨码开关的输入，用于控制底下的8个开关。
output reg …：这些是输出信号，表示模块向外部输出什么数据。
- led_en：控制哪一个数码管被启用的信号。
- led_cx：数码管上显示的内容。

内部信号和寄存器定义

wire pos_edge_s3_debounce, pos_edge_s2;
reg clk_div;
reg [31:0] cnt, cnt_s2, cnt_s3;
reg [7:0] cnt_s2_d1;
reg [7:0] display_digits [0:4];
reg [2:0] shift_reg_s2, shift_reg_s3, status;
reg [31:0] s3_counter_stable;
wire s3_stable = (s3_counter_stable >= 150000);
reg s3_sampled;
wire [3:0] num_ones = dip_switch[0] + dip_switch[1] + dip_switch[2] + dip_switch[3] + dip_switch[4] + dip_switch[5] + dip_switch[6] + dip_switch[7];

wire：这是定义的组合逻辑信号。它们用于计算逻辑结果并不能存储值。
- pos_edge_s3_debounce：用来检测 s_3 信号经过去抖动后的上升沿。
- pos_edge_s2：用来检测 s_2 信号的上升沿。
- s3_stable：表示 s_3 信号在经过15毫秒后是否稳定。
reg：这是定义的寄存器（存储单元），可以存储信号的值，并用于时序逻辑。
- clk_div：这是时钟分频器的信号，用来生成2ms的时钟。
- cnt：这是时钟的计数器，用于控制分频。
- cnt_s2、cnt_s3：分别为 s_2 和 s_3 按键计数的寄存器。
- cnt_s2_d1：记录从1到20的计数。
- display_digits [0:4]：存储要在数码管上显示的5个数字的寄存器。
- shift_reg_s2、shift_reg_s3：这是用于 s_2 和 s_3 信号的移位寄存器，用来进行边沿检测。
- s3_counter_stable：这是一个用于 s_3 信号去抖动的计数器。
num_ones：这是一个组合逻辑的输出信号，用来计算拨码开关 dip_switch 中有多少个开关是打开（‘1’）的。

上升沿检测和防抖处理

s2的上升沿检测和防抖设计

always @(posedge clk or posedge rst) begin
    if (rst)
        shift_reg_s2 <= 3'b000;
    else
        shift_reg_s2 <= {shift_reg_s2[1:0], s_2};
end
assign pos_edge_s2 = ~shift_reg_s2[2] & shift_reg_s2[1];

这个块用于检测 s2 的上升沿。shift_reg_s2 是一个移位寄存器，shift_reg_s2 <= {shift_reg_s2[1:0], s_2} 的意思是把寄存器中的每个值往前移一位，同时将最新的 s_2 信号放入最低位。pos_edge_s2 是一个组合逻辑，用于检测上升沿，只有在 shift_reg_s2[2] 是0，shift_reg_s2[1] 是1时，才会产生上升沿信号。

s3的上升沿检测和防抖设计

always @(posedge clk or posedge rst) begin
    if (rst)
        shift_reg_s3 <= 3'b000;
    else
        shift_reg_s3 <= {shift_reg_s3[1:0], s_3};
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        s3_counter_stable <= 0;
        s3_sampled <= 0;
    end else if (shift_reg_s3[1] == shift_reg_s3[2]) begin
        /* If s3 signal remains unchanged, increment debounce counter */
        if (s3_counter_stable >= 150000) begin
            s3_sampled <= shift_reg_s3[1]; /* Capture stable s3 signal after 15ms */
        end else begin
            s3_counter_stable <= s3_counter_stable + 1;
        end
    end else begin
        /* If s3 signal changes, reset debounce counter */
        s3_counter_stable <= 0;
    end
end

assign pos_edge_s3_debounce = ~s3_sampled & status[1];

这里是 s3 按键的防抖处理，防止一次按键会被多次识别。shift_reg_s3 用来记录 s3 的上升沿变化，如果 s3 保持不变，计数器 s3_counter_stable 会递增，当超过 150000 时，表示 s3 信号已经稳定超过15ms，不再有抖动。
pos_edge_s3_debounce 是通过 s3_sampled 来捕获防抖处理后的 s3 上升沿信号。

实现0.1S周期从1到20的计数器

/* Count for 0.1s interval (s2) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2 <= 0;
        else if (cnt_s2 >= FREQ_S2)
            cnt_s2 <= 0;
        else
            cnt_s2 <= cnt_s2 + 1;
    end

    /* Count from 1 to 20 */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2_d1 <= 0;
        else if (pos_edge_s2)
            cnt_s2_d1 <= 0;
        else if (cnt_s2_d1 < 20 && cnt_s2 >= FREQ_S2)
            cnt_s2_d1 <= cnt_s2_d1 + 1;
    end

手动计数器

always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s3 <= 0;
        else if (cnt_s3 < 99 && pos_edge_s3_debounce)
            cnt_s3 <= cnt_s3 + 1;
    end

数字转换为数码管格式

/* Convert digit value to 7-segment display format */
    function [7:0] digit_to_segs;
        input [3:0] digit;
        case (digit)
            4'h0: digit_to_segs = ZERO;
            4'h1: digit_to_segs = ONE;
            4'h2: digit_to_segs = TWO;
            4'h3: digit_to_segs = THREE;
            4'h4: digit_to_segs = FOUR;
            4'h5: digit_to_segs = FIVE;
            4'h6: digit_to_segs = SIX;
            4'h7: digit_to_segs = SEVEN;
            4'h8: digit_to_segs = EIGHT;
            4'h9: digit_to_segs = NINE;
            default: digit_to_segs = ZERO;
        endcase
    endfunction

这个函数的作用是将输入的4位二进制数字转换为7段显示器的对应格式，方便在实际的数字电路设计中显示相应的数字。通过case语句，可以清晰地映射输入和输出，从而实现简洁的逻辑设计。

更新显示数字

always @(posedge clk or posedge rst) begin
        if (rst) begin
            display_digits[0] <= ZERO;
            display_digits[1] <= ZERO;
            display_digits[2] <= ZERO;
            display_digits[3] <= ZERO;
            display_digits[4] <= ZERO;
        end else begin
            /* Update the display based on current counts and dip switch inputs */
            display_digits[0] <= digit_to_segs(cnt_s2_d1 % 10);
            display_digits[1] <= digit_to_segs(cnt_s2_d1 / 10 % 10);
            display_digits[2] <= digit_to_segs(cnt_s3 % 10);
            display_digits[3] <= digit_to_segs(cnt_s3 / 10 % 10);
            display_digits[4] <= digit_to_segs(num_ones);
        end
    end

时间分频

/* Clock divider (2ms) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end

    /* Generate 2ms clock */
    always @(posedge clk or posedge rst) begin
        if (rst)
            clk_div <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            clk_div <= ~clk_div;
    end

更新数码管的显示和使能信号

/* Update led_cx and led_en for 7-segment display */
    always @(posedge clk_div or posedge rst) begin
        if (rst) begin
            led_cx <= ZERO;
            led_en <= 8'b11111110;
        end else begin
            case (led_en)
                8'b01111111: led_cx <= NINE;
                8'b10111111: led_cx <= ZERO;
                8'b11011111: led_cx <= display_digits[4]; /* Display num_ones */
                8'b11101111: led_cx <= display_digits[3]; /* Tens digit of s3 press count */
                8'b11110111: led_cx <= display_digits[2]; /* Units digit of s3 press count */
                8'b11111011: led_cx <= display_digits[1]; /* Tens digit of s2_d1 */
                8'b11111101: led_cx <= display_digits[0]; /* Units digit of s2_d1 */
                8'b11111110: led_cx <= ONE;               /* Default display */
                default: led_cx <= ZERO;
            endcase
            /* Rotate the enable signal to switch between digits */
            led_en <= {led_en[0], led_en[7:1]};
        end
    end

设计文件代码勘误

勘误后完整代码

module led_display_ctrl #(
    parameter ZERO         = 8'h03,
    parameter ONE          = 8'h9f,
    parameter TWO          = 8'h25,
    parameter THREE        = 8'h0d,
    parameter FOUR         = 8'h99,
    parameter FIVE         = 8'h49,
    parameter SIX          = 8'h41,
    parameter SEVEN        = 8'h1f,
    parameter EIGHT        = 8'h01,
    parameter NINE         = 8'h09,
    parameter FREQ_CLK_DIV = 99999,    /* Clock divider for 2ms */
    parameter FREQ_S2      = 9999999   /* Frequency divider for 0.1s */
)
(
    input wire clk,
    input wire rst,
    input wire s_3,
    input wire s_2,
    input wire [7:0] dip_switch,
    output reg [7:0] led_en,
    output reg [7:0] led_cx
);

    /* Signals and registers */
    wire pos_edge_s2;              /* Rising edge signal for s2 */
    reg clk_div;                    /* Divided clock (2ms) */
    reg [31:0] cnt, cnt_s2;        /* Counters */
    reg [7:0] cnt_s2_1;            /* Counts from 1 to 20 */
    reg [7:0] dk [0:4];            /* Display data registers for 5 digits */
    
    /* Shift registers for edge detection */
    reg [2:0] shift_reg_s2;        
    reg [15:0] debounce_counter;    /* Debounce counter for s3 */
    reg s3_last;                   /* Last state of s3 */
    reg [7:0] cnt_s3;              /* Count for s3 presses */
    reg debounce_active;            /* Active flag for debounce */

    /* Count the number of dip switch bits that are '1' */
    wire [3:0] num_ones = dip_switch[0] + dip_switch[1] + dip_switch[2] + dip_switch[3] + 
                          dip_switch[4] + dip_switch[5] + dip_switch[6] + dip_switch[7];

    /* Edge detection for s2 */
    always @(posedge clk or posedge rst) begin
        if (rst)
            shift_reg_s2 <= 3'b000;
        else
            shift_reg_s2 <= {shift_reg_s2[1:0], s_2};
    end
    assign pos_edge_s2 = ~shift_reg_s2[2] & shift_reg_s2[1];

    /* Debounce logic for s3 */
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            debounce_counter <= 0;
            s3_last <= 0;
            cnt_s3 <= 0;
            debounce_active <= 0;
        end else begin
            if (s_3 && !s3_last && !debounce_active) begin
                debounce_active <= 1;
                debounce_counter <= 0;
            end
            
            if (debounce_active) begin
                debounce_counter <= debounce_counter + 1;
                
                if(debounce_counter >= 10000000) begin
                    debounce_active <= 0;
                    if (s_3) cnt_s3 <= cnt_s3 + 1;
                end
            end
            
            s3_last <= s_3;
        end
    end

    /* Count for 0.1s interval (s2) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2 <= 0;
        else if (cnt_s2 >= FREQ_S2)
            cnt_s2 <= 0;
        else
            cnt_s2 <= cnt_s2 + 1;
    end

    /* Count from 1 to 20 */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt_s2_1 <= 0;
        else if (pos_edge_s2)
            cnt_s2_1 <= 0;
        else if (cnt_s2_1 < 20 && cnt_s2 >= FREQ_S2)
            cnt_s2_1 <= cnt_s2_1 + 1;
    end

    /* Display assignment based on digit values */
    function [7:0] digit_to_segs;
        input [3:0] digit;
        case (digit)
            4'h0: digit_to_segs = ZERO;
            4'h1: digit_to_segs = ONE;
            4'h2: digit_to_segs = TWO;
            4'h3: digit_to_segs = THREE;
            4'h4: digit_to_segs = FOUR;
            4'h5: digit_to_segs = FIVE;
            4'h6: digit_to_segs = SIX;
            4'h7: digit_to_segs = SEVEN;
            4'h8: digit_to_segs = EIGHT;
            4'h9: digit_to_segs = NINE;
            default: digit_to_segs = ZERO;
        endcase
    endfunction

    /* Update display digits */
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            dk[0] <= ZERO;
            dk[1] <= ZERO;
            dk[2] <= ZERO;
            dk[3] <= ZERO;
            dk[4] <= ZERO;
        end else begin
            dk[0] <= digit_to_segs(cnt_s2_1 % 10);
            dk[1] <= digit_to_segs(cnt_s2_1 / 10 % 10);
            dk[2] <= digit_to_segs(cnt_s3 % 10);
            dk[3] <= digit_to_segs(cnt_s3 / 10 % 10);
            dk[4] <= digit_to_segs(num_ones);
        end
    end

    /* Clock divider (2ms) */
    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end

    always @(posedge clk or posedge rst) begin
        if (rst)
            clk_div <= 0;
        else if (cnt >= FREQ_CLK_DIV)
            clk_div <= ~clk_div;
    end

    /* Update led_cx and led_en */
    always @(posedge clk_div or posedge rst) begin
        if (rst) begin
            led_cx <= ZERO;
            led_en <= 8'b11111110;
        end else begin
            case (led_en)
                8'b01111111: led_cx <= NINE;
                8'b10111111: led_cx <= ZERO;
                8'b11011111: led_cx <= dk[4]; /* Display num_ones */
                8'b11101111: led_cx <= dk[3]; /* Tens digit of s3 press count */
                8'b11110111: led_cx <= dk[2]; /* Units digit of s3 press count */
                8'b11111011: led_cx <= dk[1]; /* Tens digit of s2_1 */
                8'b11111101: led_cx <= dk[0]; /* Units digit of s2_1 */
                8'b11111110: led_cx <= ONE;   /* Default display */
                default: led_cx <= ZERO;
            endcase
            led_en <= {led_en[0], led_en[7:1]}; /* Rotate the enable signal */
        end
    end
endmodule

勘误逻辑分析———基于延时法

在经过了最终实际的上板修改后,发现之前的代码还是存在一定的问题的。就是上板后手动计数器会不工作,一直显示为0。查找原因之后发现了还是对s3按键的防抖动处理这里逻辑存在问题。故修改防抖动逻辑设计(我自己的代码最终烧下来还是存在一定的抖动,但是效果还行…)

我这里采用的是延时法的一个代码实现：

/* Debounce logic for s3 */
   always @(posedge clk or posedge rst) begin
       if (rst) begin
           debounce_counter <= 0;
           s3_last <= 0;
           cnt_s3 <= 0;
           debounce_active <= 0;
       end else begin
           if (s_3 && !s3_last && !debounce_active) begin
               debounce_active <= 1;
               debounce_counter <= 0;
           end
           
           if (debounce_active) begin
               debounce_counter <= debounce_counter + 1;
               
               if(debounce_counter >= 10000000) begin
                   debounce_active <= 0;
                   if (s_3) cnt_s3 <= cnt_s3 + 1;
               end
           end
           
           s3_last <= s_3;
       end
   end

第一个if语句块是一个复位逻辑,当rst被激活的时候,所有的状态变量都置为0。

debounce_counter：计数器，用于计时。
s3_last：上一个输入信号的状态。
cnt_s3：有效按下的计数器。
debounce_active：标志，指示防抖动逻辑是否处于激活状态。

如果rst在低电平,那就正常工作。我们判断if (s_3 && !s3_last && !debounce_active) begin这个条件,决定是否激活防抖动。

如果防抖动逻辑处于活动状态（debounce_active 为1），则增加计数器 debounce_counter 的值，用于计时。

检查计数器是否达到了设定值（10000000），如果是：
将 debounce_active 设置为0，表示防抖动结束。
如果 s_3 仍为高电平，增加 cnt_s3 的值，记录有效按下的次数。

每个时钟周期结束时，将 s3_last更新为当前的 s_3 状态，以便在下一次判断时使用。

进一步优化设计文件——基于移位寄存器和计数器

用这种方法来进行消抖设计,会更稳定,效果很好。

完整代码

感谢舍友提供的这一份代码：

always @(posedge clk or posedge rst) 
    begin
        if (rst)
            s3_counter <= 0;
        else if (pos_edge_s3)
            s3_counter <= 0;
        else if (s3_counter_end)
            s3_counter <= 0;
        else
            s3_counter <= s3_counter + 1;
    end

    always @(posedge clk or posedge rst)
    begin
        if (rst)
            count_flag <= 0;
        else if (pos_edge_s3)
            count_flag <= 0;
        else if (s3_counter_end)
            begin
                if (shift_reg_s3[0])
                    count_flag <= 1;
                else
                    count_flag <= count_flag;
            end
        else
            count_flag <= count_flag;
    end

    always @(posedge clk or posedge rst)
    begin
        if (rst)
            shift_reg_s3 <= 3'b000;
        else
            shift_reg_s3 <= {shift_reg_s3[1:0],s_3};
    end

逐步逻辑分析

整体逻辑总结

历史状态存储：移位寄存器有效地保留了最近的按键状态，为上升沿检测提供了准确的依据。
稳定性判断：通过设置多周期状态判断（连续高电平）与计时器的结合，提升了对信号稳定性的检测能力。
避免误触发：只有在信号稳定并满足时间条件后，才会更新有效的按下标志，确保系统响应的可靠性。

仿真代码testbench.v

`timescale 1ns / 1ps

module led_display_ctrl_tb;

    // Parameters
    parameter CLK_PERIOD = 10; // Clock period in ns
    parameter RESET_DELAY = 20; // Reset delay in ns
    parameter DEBOUNCE_DELAY = 1000; // Simulated debounce delay for key press
    parameter JITTER_DELAY = 5; // Delay to simulate key bouncing

    // Testbench signals
    reg clk;
    reg rst;
    reg s_3;
    reg s_2;
    reg [7:0] dip_switch;
    wire [7:0] led_en;
    wire [7:0] led_cx;

    // Instantiate the DUT (Device Under Test)
    led_display_ctrl uut (
        .clk(clk),
        .rst(rst),
        .s_3(s_3),
        .s_2(s_2),
        .dip_switch(dip_switch),
        .led_en(led_en),
        .led_cx(led_cx)
    );

    // Clock generation
    initial begin
        clk = 0;
        forever #(CLK_PERIOD / 2) clk = ~clk;
    end

    // Test stimulus
    initial begin
        // Initial conditions
        rst = 1;
        s_3 = 0;
        s_2 = 0;
        dip_switch = 8'b00000000;

        // Apply reset
        #(RESET_DELAY) rst = 0;

        // Test scenario 1: Display student ID
        dip_switch = 8'b00000011; // Last two digits for example: 03
        #(100);

        // Test scenario 2: Count the number of 1's in dip switches
        dip_switch = 8'b10101010; // Should count 4
        #(100);

        // Test scenario 3: Press S3 to increment count with debouncing simulation
        #(50) s_3 = 1; // Initial press
        #(JITTER_DELAY * 3) s_3 = 0; // Release for a longer time
        #(JITTER_DELAY) s_3 = 1; // Simulate bouncing
        #(JITTER_DELAY * 2) s_3 = 0; // Release for a longer time
        #(50) s_3 = 1; // Final press
        #(50) s_3 = 0; // Release

        // Test scenario 4: Count from 0 to 20
        s_2 = 1; // Start counting
        #(100000); // Wait for some time to let it count to 20
        s_2 = 0; // Release S2

        // Test scenario 5: Reset the module
        rst = 1; // Assert reset
        #(RESET_DELAY) rst = 0; // Release reset

        // End simulation after all tests
        #(50000) $finish;
    end

    // Monitor the output signals and internal signals
    initial begin
        $monitor("Time: %t | rst: %b | s_3: %b | s_2: %b | dip_switch: %b | led_en: %b | led_cx: %b | cnt_s3: %d | debounce_counter: %d", 
                 $time, rst, s_3, s_2, dip_switch, led_en, led_cx, uut.cnt_s3, uut.debounce_counter);
    end

endmodule

约束文件

set_property PACKAGE_PIN Y18 [get_ports clk] 
set_property IOSTANDARD LVCMOS33 [get_ports clk] 

set_property PACKAGE_PIN R1 [get_ports rst] 
set_property IOSTANDARD LVCMOS33 [get_ports rst]

set_property PACKAGE_PIN P1 [get_ports s_2] 
set_property IOSTANDARD LVCMOS33 [get_ports s_2]

set_property PACKAGE_PIN P5 [get_ports s_3] 
set_property IOSTANDARD LVCMOS33 [get_ports s_3] 

set_property PACKAGE_PIN U6 [get_ports {dip_switch[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[7]}] 
set_property PACKAGE_PIN W5 [get_ports {dip_switch[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[6]}] 
set_property PACKAGE_PIN W6 [get_ports {dip_switch[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[5]}] 
set_property PACKAGE_PIN U5 [get_ports {dip_switch[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[4]}] 
set_property PACKAGE_PIN T5 [get_ports {dip_switch[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[3]}]
set_property PACKAGE_PIN T4 [get_ports {dip_switch[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[2]}]
set_property PACKAGE_PIN R4 [get_ports {dip_switch[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[1]}]
set_property PACKAGE_PIN W4 [get_ports {dip_switch[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switch[0]}]

set_property PACKAGE_PIN A18 [get_ports {led_en[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[7]}] 
set_property PACKAGE_PIN A20 [get_ports {led_en[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[6]}] 
set_property PACKAGE_PIN B20 [get_ports {led_en[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[5]}] 
set_property PACKAGE_PIN E18 [get_ports {led_en[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[4]}] 
set_property PACKAGE_PIN F18 [get_ports {led_en[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[3]}]
set_property PACKAGE_PIN D19 [get_ports {led_en[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[2]}]
set_property PACKAGE_PIN E19 [get_ports {led_en[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[1]}]
set_property PACKAGE_PIN c19 [get_ports {led_en[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_en[0]}]

set_property PACKAGE_PIN F15 [get_ports {led_cx[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[7]}] 
set_property PACKAGE_PIN F13 [get_ports {led_cx[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[6]}] 
set_property PACKAGE_PIN F14 [get_ports {led_cx[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[5]}] 
set_property PACKAGE_PIN F16 [get_ports {led_cx[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[4]}] 
set_property PACKAGE_PIN E17 [get_ports {led_cx[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[3]}]
set_property PACKAGE_PIN C14 [get_ports {led_cx[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[2]}]
set_property PACKAGE_PIN C15 [get_ports {led_cx[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[1]}]
set_property PACKAGE_PIN E13 [get_ports {led_cx[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_cx[0]}]