2024-11-05

数逻实验3——状态机实验

设计文件uart_send.v

`timescale 1ns / 1ps

module uart_send(
    input        clk,        
    input        rst,        
    input        valid,       // Data validity (1 for one clock cycle)
    input [7:0]  data,        // Data to send (8-bit student ID)
    output reg   dout         // UART TX output
);

localparam IDLE  = 2'b00;
localparam START = 2'b01;
localparam DATA  = 2'b10;
localparam STOP  = 2'b11;

reg [2:0] current_state, next_state;
reg [3:0] bit_count;         // To track bit sending
reg [15:0] baud_counter;     // For 9600 baud rate, each bit takes 10417 cycles (100MHz)
reg [7:0] data_buffer;

// State update (for current state)
always @(posedge clk or posedge rst) begin
    if (rst)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

// State transition conditions
always @(*) begin
    case (current_state)
        IDLE:   if (valid)          next_state = START;
                else                next_state = IDLE;
        START:  if (baud_counter == 10416) next_state = DATA;
                else                        next_state = START;
        DATA:   if (bit_count == 8 && baud_counter == 10416) next_state = STOP;
                else                                          next_state = DATA;
        STOP:   if (baud_counter == 10416) next_state = IDLE;
                else if (valid) begin
                    next_state = START;
                    // baud_counter <= 0;
                end
                else                        next_state = STOP;
        default:                          next_state = IDLE;
    endcase
end

// Baud rate counter (separated to its own always block)
always @(posedge clk or posedge rst) begin
    if (rst) 
        baud_counter <= 0;
    else if (valid) 
        baud_counter <= 0;
    else if (current_state != IDLE || valid) begin
        if (baud_counter == 10416) 
            baud_counter <= 0;
        else 
            baud_counter <= baud_counter + 1;
    end else 
        baud_counter <= 0;
end

// Update the buffer (separated to its own always block)
always @(posedge clk or posedge rst) begin
    if (rst) 
        data_buffer <= 0;
    else if (valid) 
        data_buffer <= data;
end

// Output and counter logic (dout and bit_count in separate always block)
always @(posedge clk or posedge rst) begin
    if (rst) begin
        dout <= 1'b1;  // Default high for idle state
        bit_count <= 0;
    end else begin
        case (current_state)
            IDLE: begin
                dout <= 1'b1;
                // baud_counter <= 0;
                if (valid) begin
                    bit_count <= 0;
                end
            end
            START: begin
                dout <= 1'b0;  // Start bit
                bit_count <= 0;
            end
            DATA: begin
                if (baud_counter == 0) begin
                    dout <= data_buffer[bit_count];  // Send bits LSB first
                    bit_count <= bit_count + 1;
                end
            end
            STOP: begin
                dout <= 1'b1;  // Stop bit
                bit_count <= 0;
            end
        endcase
    end
end

endmodule

设计文件uart_top.v

`timescale 1ns / 1ps

module uart_top(
    input clk,       // System clock input
    input rst,       // Asynchronous reset input
    output dout      // UART TX output
);

wire tx;             // Wire to hold UART transmission output
reg valid;           // Valid signal to indicate data is ready to be sent
reg [7:0] data;      // 8-bit register for data to be sent
reg [15:0] counter;  // Counter for baud rate generation
reg [31:0] delay_counter; // Counter to introduce delay between sending characters
reg [3:0] id_index;  // Index to select a character from the student_id array

// Array to store the student ID as ASCII characters
reg [7:0] student_id[0:9]; // 10-byte student ID array

// Instantiate the uart_send module
uart_send u_send(
    .clk(clk), 
    .rst(rst), 
    .data(data), 
    .valid(valid), 
    .dout(tx)
);

// Baud rate counter
// Generates timing for each bit transmission based on the 9600 baud rate.
always @(posedge clk or posedge rst) begin
    if (rst) 
        counter <= 0;
    else if (counter < 10416) 
        counter <= counter + 1;
    else 
        counter <= 0;
end

// Initialize the student ID array with ASCII values
initial begin
    student_id[0] = 8'h32; // '2'
    student_id[1] = 8'h30; // '0'
    student_id[2] = 8'h32; // '2'
    student_id[3] = 8'h33; // '3'
    student_id[4] = 8'h33; // '3'
    student_id[5] = 8'h31; // '1'
    student_id[6] = 8'h31; // '1'
    student_id[7] = 8'h34; // '4'
    student_id[8] = 8'h31; // '1'
    student_id[9] = 8'h39; // '9'
end

// State machine states
reg [3:0] state;
localparam SEND = 4'b0001;
localparam DELAY = 4'b0010;

// State machine for sending each character of the student ID with a delay
always @(posedge clk or posedge rst) begin
    if (rst) begin
        state <= SEND;            // Start in SEND state
        id_index <= 0;            // Reset index to start of student ID
        delay_counter <= 0;       // Reset delay counter
    end else begin
        case (state)
            // SEND state: loads data and initiates UART transmission
            SEND: begin
                valid <= 1;                     // Set valid to 1 to indicate data is ready to be sent
                data <= student_id[id_index];   // Load current character from student_id array
                if (valid && tx) begin          // Check if data has been sent
                    valid <= 0;                 // Reset valid after sending data
                    state <= DELAY;             // Move to DELAY state for delay between characters
                end
            end
            // DELAY state: waits a fixed time before sending the next character
            DELAY: begin
                valid <= 0;                     // Keep valid low in delay state
                if (delay_counter < 10_000_000) // 100 MHz clock with 10 million cycles is approximately 0.1 seconds
                    delay_counter <= delay_counter + 1; // Increment delay counter
                else begin
                    id_index <= (id_index + 1) % 10; // Move to the next character in student_id array
                    delay_counter <= 0;              // Reset delay counter
                    state <= SEND;                   // Return to SEND state
                end
            end
            default: 
                state <= SEND; // Default state is SEND
        endcase
    end
end

// Connect tx from uart_send to dout output
assign dout = tx;

endmodule

仿真文件uart_send_tb.v

`timescale 1ns / 1ps

module uart_send_tb;

reg clk;
reg rst;
reg valid;
reg [7:0] data;
wire dout;

uart_send u_uart_send (
    .clk(clk),
    .rst(rst),
    .valid(valid),
    .data(data),
    .dout(dout)
);

localparam CLOCK_FREQ = 100*1e6;         //clock freq: 100MHz
localparam PERIOD     = 1e9/CLOCK_FREQ;  // clock ycle: 10ns
localparam BAUD_RATE  = 9600;
localparam DIVIDER    = CLOCK_FREQ / BAUD_RATE -1; // 9600:10416, 115200:867,


always #(PERIOD/2) clk = ~clk;


integer bit_index = 0;    
reg [9:0] expected_bits; 
reg [3:0] all_check_error; 
reg check_error;         


initial begin
    clk   = 0;
    rst   = 1'b1;
    valid = 1'b0;
    data  = 8'h00;
    check_error     = 1'b0; 
    all_check_error = 1'b0; 
    expected_bits   = 10'h0;
    #(10*PERIOD);

    rst = 1'b0;
    #(2*PERIOD);

    // test case1: 8'hA5 (10100101)
    data  = 8'hA5;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;     // valid should last one clock
    valid = 1'b0;
    check_uart_output(8'hA5);   
    #(100*PERIOD);

    // test case2: 8'h3C (00111100)
    data  = 8'h3C;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0};  
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(20000*PERIOD);

    // test case3: 8'hFF (11111111)
    data  = 8'hFF;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    data  = 8'h00;
    check_uart_output(8'hFF);   
    #(10000*PERIOD);

    // test case4: 8'h00 (00000000)
    data  = 8'h00;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(10*PERIOD);  

    // test case5: 8'h5A (01011010)
    data  = 8'h5A;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(100*PERIOD);

    if (!all_check_error)
        $display("All tests passed successfully!");
    else
        $display("%d test failed!", all_check_error);

    $display("Uart baud rate = %d, freq divider = %d",BAUD_RATE, DIVIDER);
    $finish;
end


task check_uart_output;
    input [7:0]       i_data ;
    begin
        $display("Test case :%x start", i_data);
        bit_index   = 0;
        check_error = 0;
        repeat (10) begin         // total 10 bits
            #(DIVIDER*PERIOD);    // time for one bit
            if (dout !== expected_bits[bit_index]) begin
                $display("Error at time %t, %d th bit: Expected %b, Got %b", $time, bit_index, expected_bits[bit_index], dout);
                check_error = 1'b1;
            end
            bit_index = bit_index + 1; 
        end
        if (check_error) begin
            all_check_error = all_check_error + 1'b1; 
            $display("Test case %x failed\n", i_data);
        end 
        else $display("Test case %x success\n", i_data);
    end
endtask

endmodule

仿真文件top_tb.v

module top_tb(
);

reg clk;
reg rst;
wire dout;

uart_top ut (
    .clk(clk),
    .rst(rst),
    .dout(dout)
);

always #5 clk = ~clk;

initial begin
    clk = 0;
    rst = 1;
    #10;
    rst = 0;
    
    #1000000000;
    $finish;
end
endmodule

约束文件pin.xdc

1
2
3

set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports  dout];
set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports  clk];
set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports  rst];

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本文作者： Arua
本文链接： https://blog.visionary-5.top/2024/11/05/%E6%95%B0%E9%80%BB%E5%AE%9E%E9%AA%8C3%E2%80%94%E2%80%94%E7%8A%B6%E6%80%81%E6%9C%BA%E5%AE%9E%E9%AA%8C/
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