数逻实验4——综合实验

---

顶层文件uart_top.v

`timescale 1ns / 1ps

module uart_top(
    input wire rst,
    input wire clk,
    input wire button,
    input wire uart_rx,
    input wire [7:0] data_in,
    output wire [7:0] led_cx,
    output wire [7:0] led_en,
    output wire uart_tx
);

    wire tx;
    wire [7:0] DATA;
    wire send_valid;
    wire recv_valid;
    wire [7:0] u_led_cx;
    wire [7:0] u_led_en;

    uart_recv u_uart_recv (
        .rst(rst),
        .clk(clk),
        .valid(recv_valid),
        .data(DATA),
        .din(uart_rx)
    );

    button_detect u_button_detect (
        .rst(rst),
        .clk(clk),
        .valid(send_valid),
        .button(button)
    );

    uart_send u_uart_send(
        .rst(rst),
        .clk(clk),
        .valid(send_valid),
        .data(data_in),
        .dout(tx)
    );

    led_controller u_led_controller(
        .rst(rst),
        .clk(clk),
        .valid(recv_valid),
        .data(DATA),
        .led_cx(u_led_cx),
        .led_en(u_led_en)
    );

    assign led_cx = u_led_cx;
    assign led_en = u_led_en;
    assign tx = uart_tx;
    
endmodule

模块uart_recv.v

`timescale 1ns / 1ps

module uart_recv(
    input        clk,        
    input        rst,        
    input        din,          // Serial data input (from UART receiver)
    output reg   valid,        // Output signal indicating valid received data
    output reg [7:0] data      // Output register to store received data (8-bit)
);

localparam IDLE  = 3'b000;   // State: IDLE (waiting for start bit)
localparam START = 3'b001;   // State: START (start bit detected)
localparam DATA  = 3'b010;   // State: DATA (receiving data bits)
localparam STOP  = 3'b011;   // State: STOP (stop bit detected)

reg [3:0] current_state, next_state; // Registers to hold the current and next states
reg [3:0] bit_count;                 // Count of received data bits (0-7)
reg [15:0] cnt;                      // Counter for baud rate timing
reg [7:0] data_buffer;              // Buffer to store the received data

parameter CNT_HALF = 5208;          // Half baud rate cycle time (for bit sampling)
parameter CNT_END = 10416;          // Full baud rate cycle time (for detecting end of bit)

// State update on rising edge of clock or reset
always @(posedge clk or posedge rst) begin
    if (rst) 
        current_state <= IDLE;     // Reset to IDLE state on reset signal
    else
        current_state <= next_state;  // Update to the next state
end

// State transition conditions based on current state and other signals
always @(*) begin
    case (current_state)
        IDLE:   if (~din)           next_state = START;  // Transition to START on detecting falling edge of din (start bit)
                else                 next_state = IDLE;   // Stay in IDLE if no start bit
        START:  if (cnt == CNT_END) next_state = DATA;   // Transition to DATA after one bit period (CNT_END)
                else                 next_state = START;  // Stay in START if counting is not complete
        DATA:   if (bit_count == 8 && cnt == CNT_END) next_state = STOP;  // Transition to STOP after 8 data bits
                else                 next_state = DATA;   // Stay in DATA while receiving bits
        STOP:   if (cnt == CNT_END) next_state = IDLE;    // Transition back to IDLE after stop bit
                else                 next_state = STOP;   // Stay in STOP until the stop bit period ends
        default: next_state = IDLE;   // Default state is IDLE
    endcase
end

// Baud rate counter to manage timing for each bit period
always @(posedge clk or posedge rst) begin
    if (rst) 
        cnt <= 0;  // Reset counter on reset signal
    else if (current_state != next_state) 
        cnt <= 0;  // Reset counter on state change
    else if (cnt == CNT_END) 
        cnt <= 0;  // Reset counter when it reaches the end of one bit period
    else 
        cnt <= cnt + 1;  // Increment counter to track bit period timing
end

// Output and counter logic based on current state
always @(posedge clk or posedge rst) begin
    if (rst) begin
        valid <= 0;           // Invalid data on reset
        bit_count <= 0;       // Reset bit counter
        data <= 8'b00000000;  // Clear data register
        data_buffer <= 8'b00000000;  // Clear data buffer
    end else begin
        case (current_state)
            IDLE: begin
                valid <= 0;  // No valid data in IDLE state
            end
            START: begin
                bit_count <= 0;  // Reset bit counter at the start of data reception
            end
            DATA: begin
                if (cnt == CNT_HALF) begin
                    data_buffer[bit_count] <= din;  // Sample the input bit at half the bit period
                    bit_count <= bit_count + 1;     // Increment bit count after each received bit
                end
            end
            STOP: begin
                if (cnt == CNT_END) begin
                    valid <= 1;         // Mark the data as valid after receiving the stop bit
                    data <= data_buffer; // Store received data in the output register
                end else begin
                    valid <= 0;         // Clear valid signal before stop bit period is over
                end
                bit_count <= 0;           // Reset bit count after receiving stop bit
            end
        endcase
    end
end

endmodule

模块uart_send.v

`timescale 1ns / 1ps

module uart_send(
    input        clk,        
    input        rst,        
    input        valid,       // Data validity (1 for one clock cycle)
    input [7:0]  data,        // Data to send (8-bit student ID)
    output reg   dout         // UART TX output
);

localparam IDLE  = 2'b00;
localparam START = 2'b01;
localparam DATA  = 2'b10;
localparam STOP  = 2'b11;

reg [2:0] current_state, next_state;
reg [3:0] bit_count;         // To track bit sending
reg [15:0] baud_counter;     // For 9600 baud rate, each bit takes 10417 cycles (100MHz)
reg [7:0] data_buffer;

// State update (for current state)
always @(posedge clk or posedge rst) begin
    if (rst)
        current_state <= IDLE;
    else
        current_state <= next_state;
end

// State transition conditions
always @(*) begin
    case (current_state)
        IDLE:   if (valid)          next_state = START;
                else                next_state = IDLE;
        START:  if (baud_counter == 10416) next_state = DATA;
                else                        next_state = START;
        DATA:   if (bit_count == 8 && baud_counter == 10416) next_state = STOP;
                else                                          next_state = DATA;
        STOP:   if (baud_counter == 10416) next_state = IDLE;
                else if (valid) begin
                    next_state = START;
                    // baud_counter <= 0;
                end
                else                        next_state = STOP;
        default:                          next_state = IDLE;
    endcase
end

// Baud rate counter (separated to its own always block)
always @(posedge clk or posedge rst) begin
    if (rst) 
        baud_counter <= 0;
    else if (valid) 
        baud_counter <= 0;
    else if (current_state != IDLE || valid) begin
        if (baud_counter == 10416) 
            baud_counter <= 0;
        else 
            baud_counter <= baud_counter + 1;
    end else 
        baud_counter <= 0;
end

// Update the buffer (separated to its own always block)
always @(posedge clk or posedge rst) begin
    if (rst) 
        data_buffer <= 0;
    else if (valid) 
        data_buffer <= data;
end

// Output and counter logic (dout and bit_count in separate always block)
always @(posedge clk or posedge rst) begin
    if (rst) begin
        dout <= 1'b1;  // Default high for idle state
        bit_count <= 0;
    end else begin
        case (current_state)
            IDLE: begin
                dout <= 1'b1;
                // baud_counter <= 0;
                if (valid) begin
                    bit_count <= 0;
                end
            end
            START: begin
                dout <= 1'b0;  // Start bit
                bit_count <= 0;
            end
            DATA: begin
                if (baud_counter == 0) begin
                    dout <= data_buffer[bit_count];  // Send bits LSB first
                    bit_count <= bit_count + 1;
                end
            end
            STOP: begin
                dout <= 1'b1;  // Stop bit
                bit_count <= 0;
            end
        endcase
    end
end

endmodule

模块button_detect.v

`timescale 1ns / 1ps

module button_detect(
    input wire rst,
    input wire clk,
    input wire button,
    output reg valid
);

    // the button_detect is responsible for debouncing the button and send a single-clock-cycle 'valid' signal to uart_send
    reg [15:0] debounce_counter;
    reg button_last;
    reg debounce_active;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            debounce_counter <= 0;
            button_last <= 0;
            debounce_active <= 0;
            valid <= 0;
        end else begin
            if (button && !button_last && !debounce_active) begin
                debounce_active <= 1;
                debounce_counter <= 0;
            end

            if (debounce_active) begin
                debounce_counter <= debounce_counter + 1;

                if (debounce_counter >= 20000) begin
                    debounce_active <= 0;
                    if (button) begin
                        valid <= 1;
                    end
                end
            end else valid <= 0;

            button_last <= button;
        end
    end

endmodule

模块led_controller.v

`timescale 1ns / 1ps

module led_controller(
    input wire clk,
    input wire rst,
    input wire valid, // once the uart_recv finish, it send a 'valid'
    input wire [7:0] data,
    output reg [7:0] led_en,
    output reg [7:0] led_cx
);
    // the codes of correspond numbers
    reg [7:0] codes[0:15];
    always @(*) begin
        codes[0] <= 8'b00000011;
        codes[1] <= 8'b10011111;
        codes[2] <= 8'b00100101;
        codes[3] <= 8'b00001101;
        codes[4] <= 8'b10011001;
        codes[5] <= 8'b01001001;
        codes[6] <= 8'b01000001;
        codes[7] <= 8'b00011111;
        codes[8] <= 8'b00000001;
        codes[9] <= 8'b00001001;
        codes[10] <= 8'b00010001;
        codes[11] <= 8'b11000001;
        codes[12] <= 8'b11100101;
        codes[13] <= 8'b10000101;
        codes[14] <= 8'b01100001;
        codes[15] <= 8'b01110001;
    end

    reg [3:0] data_for_display;
    always @(*) begin
        case (data)
            48:  data_for_display <= 0;
            49:  data_for_display <= 1;
            50:  data_for_display <= 2;
            51:  data_for_display <= 3;
            52:  data_for_display <= 4;
            53:  data_for_display <= 5;
            54:  data_for_display <= 6;
            55:  data_for_display <= 7;
            56:  data_for_display <= 8;
            57:  data_for_display <= 9;
            65:  data_for_display <= 10;
            66:  data_for_display <= 11;
            67:  data_for_display <= 12;
            68:  data_for_display <= 13;
            69:  data_for_display <= 14;
            70:  data_for_display <= 15;
            97:  data_for_display <= 10;
            98:  data_for_display <= 11;
            99:  data_for_display <= 12;
            100:  data_for_display <= 13;
            101:  data_for_display <= 14;
            102:  data_for_display <= 15;

            default: data_for_display <= 0;
        endcase
    end


    // the value of each digit(DK)
    reg [3:0] digit_values[0:7];
    reg [3:0] highest_bit; // use to indicate the empty digit

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            highest_bit <= 3'b001;
            digit_values[0] <= 4'b0000;
            digit_values[1] <= 4'b0000;
            digit_values[2] <= 4'b0000;
            digit_values[3] <= 4'b0000;
            digit_values[4] <= 4'b0000;
            digit_values[5] <= 4'b0000;
            digit_values[6] <= 4'b0000;
            digit_values[7] <= 4'b0000;
        end else if (valid) begin
            if (highest_bit > 7) digit_values[7] <= digit_values[6];
            if (highest_bit > 6) digit_values[6] <= digit_values[5];
            if (highest_bit > 5) digit_values[5] <= digit_values[4];
            if (highest_bit > 4) digit_values[4] <= digit_values[3];
            if (highest_bit > 3) digit_values[3] <= digit_values[2];
            if (highest_bit > 2) digit_values[2] <= digit_values[1];
            if (highest_bit > 1) digit_values[1] <= digit_values[0];
            digit_values[0] <= data_for_display;
    
            if (highest_bit <= 8) highest_bit <= highest_bit + 1;
        end
    end

    // the display of leds
    reg [15:0] refresh_counter;
    reg [2:0] current_digit;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            refresh_counter <= 0;
            current_digit <= 0;
            led_en <= 8'b00000000;
            led_cx <= 8'b00000000;
        end else begin
            if (refresh_counter < 20000) begin
                refresh_counter <= refresh_counter + 1;
            end else begin
                refresh_counter <= 0;
                current_digit <= current_digit + 1;
                if(current_digit > 7) current_digit <= 0;
            end

            led_en <= ~(8'b00000001 << current_digit);

            if (current_digit >= highest_bit - 1) begin
                led_cx <= 8'b11111111; // display nothing
            end else begin
                led_cx <= codes[digit_values[current_digit]];
            end
            
        end
    end
endmodule 

仿真

`timescale 1ns / 1ps

module uart_top_tb();

    reg clk;
    reg rst;
    reg button;
    reg [7:0] data;
    wire [7:0] led_cx;
    wire [7:0] led_en;

    uart_top u_uart_top(
        .clk(clk),
        .rst(rst),
        .button(button),
        .data_in(data),
        .led_cx(led_cx),
        .led_en(led_en)
    );

    always #5 clk = ~clk;

    initial begin
        clk = 0;
        rst = 1;
        data <= 8'b00000000;
        button <= 0;
        #10;

        rst = 0;

        #1000;
//1
        data <= 8'b00000011;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//2
        data <= 8'b00000010;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//3
        data <= 8'b00000111;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//4
        data <= 8'b00000101;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//5
        data <= 8'b00000110;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//6
        data <= 8'b00000111;
        button <= 1;
        #1000000
        button <= 0;

        #10000000;
//7
        data <= 8'b00001111;
        button <= 1;
        #1000000
        button <= 0;

//8
        #10000000;

        data <= 8'b00001000;
        button <= 1;
        #1000000
        button <= 0;
//9
        #10000000;

        data <= 8'b00001011;
        button <= 1;
        #1000000
        button <= 0;



        $finish;
    end

endmodule

`timescale 1ns / 1ps

module uart_receive_tb();

    localparam CLK_FREQ = 100_000_000;          // clock frequency: 100 MHz
    localparam PERIOD   = 1e9/CLK_FREQ;         // clock cycle: 10ns
    localparam BAUD_RATE = 9600;      
    localparam DIVIDER = CLK_FREQ / BAUD_RATE;  // clocks for one bit, should be 10416

    reg         clk;
    reg         rst;
    reg         din;
    wire        valid;
    wire [7:0]  data;
     
    uart_recv u_uart_recv (
        .clk(clk),
        .rst(rst),
        .din(din),
        .valid(valid),
        .data(data)
    );

    always #(PERIOD/2) clk = ~clk;

    reg [7:0] test_data[0:9];   // 10 test cases
    integer i;                 
    integer err_num;

    initial begin
        $display("Uart baud rate = %d, freq divider = %d",BAUD_RATE, DIVIDER);

        test_data[0] = 8'h55;  // 0101_0101
        test_data[1] = 8'hA3;  // 1010_0011
        test_data[2] = 8'h0F;  // 0000_1111
        test_data[3] = 8'hF0;  // 1111_0000
        test_data[4] = 8'h33;  // 0011_0011
        test_data[5] = 8'hCC;  // 1100_1100
        test_data[6] = 8'hFF;  // 1111_1111
        test_data[7] = 8'h00;  // 0000_0000
        test_data[8] = 8'h5A;  // 0101_1010
        test_data[9] = 8'hA5;  // 1010_0101
        
        #(200*DIVIDER*PERIOD)
        $display("Test failed: Timeout ");
        $finish;
    end

    initial begin
        clk = 0;
        rst = 1;
        din = 1; 
        err_num = 0;
        #(10*PERIOD) rst = 0; 
        
        for (i = 0; i < 10; i = i + 1) begin
            send_byte(test_data[i]);  

            wait (valid == 1);
            if (data === test_data[i]) begin
                $display("Test case:%2d success, Received expected data = 0x%h", i, data);
            end else begin
                err_num = err_num + 1;
                $display("Test case:%2d failed, Expected 0x%h, but received 0x%h", i, test_data[i], data);
            end
            #(DIVIDER*PERIOD/2);
        end

        if(err_num == 0)  $display("All test cases passed.");
        else              $display("%2d test cases failed.", err_num);
        
        #(10*PERIOD)
        $finish;
    end


    task send_byte(input [7:0] byte);
        integer j;
        begin
            din = 0;  // start bit
            #(DIVIDER*PERIOD);

            for (j = 0; j < 8; j = j + 1) begin    // 8bit data
                din = byte[j];
                #(DIVIDER*PERIOD);
            end

            din = 1;    // stop bit
            #(DIVIDER*PERIOD/2);
        end
    endtask

endmodule

`timescale 1ns / 1ps

module uart_send_tb;

reg clk;
reg rst;
reg valid;
reg [7:0] data;
wire dout;

uart_send u_uart_send (
    .clk(clk),
    .rst(rst),
    .valid(valid),
    .data(data),
    .dout(dout)
);

localparam CLOCK_FREQ = 100*1e6;         //clock freq: 100MHz
localparam PERIOD     = 1e9/CLOCK_FREQ;  // clock ycle: 10ns
localparam BAUD_RATE  = 9600;
localparam DIVIDER    = CLOCK_FREQ / BAUD_RATE -1; // 9600:10416, 115200:867,


always #(PERIOD/2) clk = ~clk;


integer bit_index = 0;    
reg [9:0] expected_bits; 
reg [3:0] all_check_error; 
reg check_error;         


initial begin
    clk   = 0;
    rst   = 1'b1;
    valid = 1'b0;
    data  = 8'h00;
    check_error     = 1'b0; 
    all_check_error = 1'b0; 
    expected_bits   = 10'h0;
    #(10*PERIOD);

    rst = 1'b0;
    #(2*PERIOD);

    // test case1: 8'hA5 (10100101)
    data  = 8'hA5;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;     // valid should last one clock
    valid = 1'b0;
    check_uart_output(8'hA5);   
    #(100*PERIOD);

    // test case2: 8'h3C (00111100)
    data  = 8'h3C;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0};  
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(20000*PERIOD);

    // test case3: 8'hFF (11111111)
    data  = 8'hFF;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    data  = 8'h00;
    check_uart_output(8'hFF);   
    #(10000*PERIOD);

    // test case4: 8'h00 (00000000)
    data  = 8'h00;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(10*PERIOD);  

    // test case5: 8'h5A (01011010)
    data  = 8'h5A;
    valid = 1'b1;
    expected_bits = {1'b1, data, 1'b0}; 
    #PERIOD;
    valid = 1'b0;
    check_uart_output(data);   
    #(100*PERIOD);

    if (!all_check_error)
        $display("All tests passed successfully!");
    else
        $display("%d test failed!", all_check_error);

    $display("Uart baud rate = %d, freq divider = %d",BAUD_RATE, DIVIDER);
    $finish;
end


task check_uart_output;
    input [7:0]       i_data ;
    begin
        $display("Test case :%x start", i_data);
        bit_index   = 0;
        check_error = 0;
        repeat (10) begin         // total 10 bits
            #(DIVIDER*PERIOD);    // time for one bit
            if (dout !== expected_bits[bit_index]) begin
                $display("Error at time %t, %d th bit: Expected %b, Got %b", $time, bit_index, expected_bits[bit_index], dout);
                check_error = 1'b1;
            end
            bit_index = bit_index + 1; 
        end
        if (check_error) begin
            all_check_error = all_check_error + 1'b1; 
            $display("Test case %x failed\n", i_data);
        end 
        else $display("Test case %x success\n", i_data);
    end
endtask

endmodule

约束文件pin.xdc

set_property -dict {PACKAGE_PIN Y18  IOSTANDARD LVCMOS33} [get_ports clk]
set_property -dict {PACKAGE_PIN R1  IOSTANDARD LVCMOS33} [get_ports rst]
set_property -dict {PACKAGE_PIN P1  IOSTANDARD LVCMOS33} [get_ports button]
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports  uart_rx];  
set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports  uart_tx];
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports led_en[0]]
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports led_en[1]]
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports led_en[2]]
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports led_en[3]]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports led_en[4]]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports led_en[5]]
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports led_en[6]]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports led_en[7]]
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports led_cx[0]]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports led_cx[1]]
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports led_cx[2]]
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports led_cx[3]]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports led_cx[4]]
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports led_cx[5]]
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports led_cx[6]]
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports led_cx[7]]
set_property -dict {PACKAGE_PIN W4  IOSTANDARD LVCMOS33} [get_ports data_in[0]]
set_property -dict {PACKAGE_PIN R4  IOSTANDARD LVCMOS33} [get_ports data_in[1]]
set_property -dict {PACKAGE_PIN T4  IOSTANDARD LVCMOS33} [get_ports data_in[2]]
set_property -dict {PACKAGE_PIN T5  IOSTANDARD LVCMOS33} [get_ports data_in[3]]
set_property -dict {PACKAGE_PIN U5  IOSTANDARD LVCMOS33} [get_ports data_in[4]]
set_property -dict {PACKAGE_PIN W6  IOSTANDARD LVCMOS33} [get_ports data_in[5]]
set_property -dict {PACKAGE_PIN W5  IOSTANDARD LVCMOS33} [get_ports data_in[6]]
set_property -dict {PACKAGE_PIN U6  IOSTANDARD LVCMOS33} [get_ports data_in[7]]

-------------本文结束感谢您的阅读-------------

本文作者： Arua
本文链接： https://blog.visionary-5.top/2024/11/13/%E6%95%B0%E9%80%BB%E5%AE%9E%E9%AA%8C4-%E7%BB%BC%E5%90%88%E5%AE%9E%E9%AA%8C%EF%BC%88%E5%AE%9E%E7%8E%B0%E6%8E%A5%E6%94%B6%E5%8F%91%E9%80%81%E5%8A%9F%E8%83%BD%EF%BC%89/
版权声明： 本作品采用 知识共享署名-非商业性使用-相同方式共享 4.0 国际许可协议 进行许可。转载请注明出处！

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